-------------------------------------------- -- -- rsca.vhd -- -- Description: Top level of two-channel PWM motor driver chip -- -- Revision history: -- 21Apr2009 DF Made into drive from tile -- 22Apr2009 DF Compiling, fixing signal names -- 04May2009 DF Adding servo module -- 09May2009 DF Adding switch signals, renumbered channels 1-6 -- 15May2009 DF Debugging pwm now, moving logic analyzer stuff -- 19Dec2009 DF Copying to esc2 -- 20Mar2010 DF Copied to rsca, debugging hardware -- -- Description: -- This chip provides two PWM motor and two up/off -- control outputs from an 8 bit data bus. -- The two PWM motor drives are configured for sequential drive. -- Sequential drive allow use of 48V of battery voltage to run -- four 12V motors at 25% duty cycle with non-overlapping PWM. -------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity drive is port ( -- universal inputs clock_i : in std_logic; reset_i : in std_logic; -- bus interface data_i : in std_logic_vector(7 downto 0); load_i : in std_logic; phase_i : in std_logic; slot_i : in std_logic; -- interface to four motor drivers hia_o : out std_logic_vector(2 downto 1); hib_o : out std_logic_vector(2 downto 1); loa_o : out std_logic_vector(2 downto 1); lob_o : out std_logic_vector(2 downto 1); fault_i : in std_logic_vector(2 downto 1); -- switch output for two channels switch1_o : out std_logic; switch2_o : out std_logic ); end entity drive; architecture behavioral of drive is component busin port ( clock_i : in std_logic; reset_i : in std_logic; -- bus interface data_i : in std_logic_vector(7 downto 0); load_i : in std_logic; slot_i : in std_logic; phase_i : in std_logic; -- pwm engine interface dir : out std_logic; speed : out std_logic_vector(6 downto 0); load : out std_logic_vector(2 downto 1); start : out std_logic_vector(2 downto 1); -- output data switch1_o : out std_logic; switch2_o : out std_logic ); end component; signal reset : std_logic; signal dir : std_logic; signal speed : std_logic_vector(6 downto 0); signal load : std_logic_vector(2 downto 1); signal start : std_logic_vector(2 downto 1); component pwm port ( clk : in std_logic; rst : in std_logic; speed : in std_logic_vector(6 downto 0); dir : in std_logic; load : in std_logic; start : in std_logic; hia : out std_logic; hib : out std_logic; loa : out std_logic; lob : out std_logic; fault : in std_logic ); end component; begin BUSIN_COMPONENT: busin port map ( clock_i => clock_i, reset_i => reset, data_i => data_i, load_i => load_i, dir => dir, speed => speed, load => load, phase_i => phase_i, slot_i => slot_i, start => start, switch1_o => switch1_o, switch2_o => switch2_o ); -- Create two PWM units pwm1: for i in 1 to 2 generate pwm_group: pwm port map ( clk => clock_i, rst => reset, speed => speed, dir => dir, load => load(i), start => start(i), hia => hia_o(i), hib => hib_o(i), loa => loa_o(i), lob => lob_o(i), fault => fault_i(i) ); end generate; -- Define misc connections reset <= not(reset_i); end behavioral;